1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly a semiconductor memory device including a multi-bit test circuit and a method thereof.
2. Description of the Related Art
In general, a semiconductor memory device, for example, a high density dynamic RAM (Random Access Memory) includes a multi-bit test circuit. Further, it is well known that four input/output pins (though not necessarily) are commonly used in a multi-bit test mode, while eight input/output pins are used in a normal read/write mode. The number of the input/output pins used in the multi-bit test mode should be as small as possible, in order to simultaneously obtain fail information of a plurality of memory cells. In other words, with use of the four input/output pins, sixteen memory cells are accessible simultaneously to write test data bits therein. Then, the written test data bits in the same block are read out and compared to one another to generate a comparison data. The comparison data is transferred to the associated input/output pin. As a result, it is possible to check the fail bits of more memory cells, with use of the less input/output pins. As described in the foregoing, the multi-bit test is able to detect fail bits of more memory cells within a limited short time. Thus, it is possible to quickly test the performance of a dynamic RAM at a low cost. Such multi-bit test circuit is disclosed in U.S. Pat. No. 5,029,330 entitled "Semiconductor Memory Device", issued to Kajigaya et. al. on Jul. 2, 1991.
FIG. 1, discloses a prior art multi-bit test circuit. For the convenience of explanation, the input/output pins used in the multi-bit test mode of operation will be referred to as multi-bit input/output pins. Commonly, one or more multi-bit input/output pins are used for the multi-bit test. Further, the multi-bit test can be performed on a device in a package state or a wafer state. In the following descriptions, the multi-bit test is performed in a wafer state with use of four multi-bit input/output pins, in order to secure the more effective multi-bit test.
As illustrated in FIG. 1, a memory cell array is divided into sub-arrays 100 and 101. The sub-array 100 is again divided into blocks BLK0 and BLK1, and the sub-array 101 into BLK2 and BLK3. The blocks BLKO-BLK3 include memory cells C1-C4, C5-C8, C9-C12, and C13-C16, respectively, which are connected to intersections of bit lines BL1-BL4 and word lines WL0-WL3. Moreover, redundant word lines RWL0-RWL3 for replacing fail word lines are arranged in the vicinity of the blocks BLK0-LK3, respectively. The bit lines BL1-BL4 are connected to one end of sense amplifier drivers 103-110, respectively. The sense amplifier drivers 103-110 transfer data on multi-bit input/output pins TIO0, TIO2, TIO4, and TIO6 to the memory cells via the bit lines BL1-BL4, and/or read out the data stored into the memory cells. The other ends of the sense amplifier drivers 103-110 are connected to outputs from input buffers 115-118, respectively. The input buffers 115-118 transfer the data on the multi-bit input/output pins TIO0, TIO2, TIO4, and TIO6 to the sense amplifier drivers 103-110, in response to a multi-bit test enable signal MBTE. The other ends of the sense amplifier drivers 103-110 are also connected to comparators 111-114, respectively. The comparators 111-114 compare and compress the amplified signal outputs from the sense amplifier drivers 103-110 in response to the multi-bit test enable signal MBTE, and transfer the comparison data to the multi-bit input/output pins TIO0, TIO2, TIO4, and TIO6, respectively. In the light of the comparison data output from the comparators 111-114, the multi-bit test circuit detects a block including the fail memory cell. As described above, the multi-bit test operation is performed by means of a plurality of sub-arrays, sense amplifiers, input buffers, comparators, and input/output pins.
In the normal mode of operation, eight input/output pins IO0-IO7 are used for reading/writing data. Binary data (or data bits) received from the input/output pins IO0-IO7 are written into the memory cells C1-C16. Then, the written data are read out through the input/output pins IO0-IO7 by means of the above described circuits. Meanwhile, in the multi-bit test mode of operation, the same test data bit is simultaneously written into the four memory cells in each block via the associated multi-bit input/output pin. Then, the test data bits written into the memory cells in the same block are read out and compared to one another to check whether or not they are identical. Therefore, only four or less than four multi-bit input/output pins, which are less than the number of input/output pins used in the normal read/write mode, are used in the multi-bit test mode.
Meanwhile, the comparators 111-114 connected to the sense amplifier drivers 103-110 compare the test data bits stored into the memory cells in the same blocks in response to the multi-bit test enable signal MBTE, to generate flag data "1" or "0" at the multi-bit input/output pins. Based on the flag data appearing at the multi-bit input/output pins, it is possible to check whether or not the blocks include the fail memory cells, and to obtain positional information about the fail bits. For example, in the case where the flag data "0" is generated from the comparator 111 to the multi-bit input/output pin TIO0, the scheme recognizes that at least one of the memory cells C5-C8 connected to the word line WL1 in the block BLK1 is the fail cell, and replaces the fail word line WL1 with the redundant word line RWL1. However, as described above, the prior art multi-bit test circuit writes the same test data bits into all the memory cells connected to the same word line. For example, the same test data bit on the multi-bit input/output pins TIO0 is written into the memory cells C5-C8 in the block BLK1. Therefore, in the case where the memory cell C5 cannot store the test data bit due to the fail, the comparator 111 can misrecognize the output data of the memory cell C5 as having the same phase as that of the memory cell C6, if a short bridge exists between the bit lines BL1 and BL2. In this case, the fail of the memory cell C5 cannot be detected. In the end, such prior art multi-bit test circuit has a problem that the fail cell might not be accurately detected when there exists the short bridge between the bit lines.